FOR IMMEDIATE RELEASE
CHELSIO ANNOUNCES 4TH GENERATION TERMINATOR CHIP
Feature-Rich T4 ASIC Offloads TOE, FCoE, iSCSI, iWARP To Enable Converged Networks Over Single Unified Wire
SUNNYVALE, CA – March 22, 2010 – Chelsio Communications, Inc., the leading provider of 10-Gigabit Ethernet (10GbE) adapters, ASICs, and storage solutions, today announced its fourth generation high performance 10Gb Ethernet silicon technology. The Terminator is Chelsio’s flagship architecture, an industry- proven, protocol-rich 10Gb ASIC that has secured more than 100 OEM platform wins and is widely deployed with more than 100,000 ports worldwide.
Targeted at LAN-on-motherboard (LOM) design opportunities, the Terminator 4 (T4) is a highly integrated, highly virtualized 10GbE controller built around a programmable protocol-processing engine. T4 includes Chelsio’s fourth-generation TCP offload (TOE) design, third generation iSCSI design, and second-generation iWARP (RDMA) implementation. In addition to full TCP and iSCSI offload, the T4 also supports full Fibre Channel over Ethernet (FCoE) offload.
The T4 is the industry’s first single-chip solution to concurrently support TOE, iSCSI, FCoE and iWARP offload. Ideal for all high performance clustering applications, storage networks and data networks, the T4 enables the unified wire by simultaneously allowing wire-speed IP traffic, InfiniBand and FibreChannel applications to run over Ethernet unmodified.
“The Terminator 4 is an impressive ASIC, capable of offloading network, storage and clustering protocols while also including key virtualization features,” said Bob Wheeler, senior analyst at The Linley Group. “The convergence of network traffic around 10Gb Ethernet is happening now and the availability of a universal 10GbE controller like the Terminator should help accelerate this trend.”
T4 Architectural Features
The T4 is a 10GbE controller built around a programmable protocol-processing engine. Much of the processing of the offloaded protocols is implemented in microcode running on a pipe-lined VLIW engine. To minimize latency, the pipeline supports simultaneous cut-through operation for both transmit and receive paths. This processing architecture also provides for wire-speed operation at small packet size and regardless of the number of TCP connections.
For server connections, the T4 integrates a PCI Express v2.0 x8 host interface, and with support for the 5Gbps Gen2 data rate, the PCIe interface provides up to 32Gbps of bandwidth to the server. The T4 also adds support for PCIe I/O virtualization.
On the network side, the T4 integrates four Ethernet ports that support GbE as well as 10GbE operation. With embedded 10GbE serdes, all four ports provide direct support for 10GBASE-KR and two ports support the four-lane 10GBASE-CX4/KX4 interfaces. For GbE operation, all four ports offer a choice of SGMII or 1000BASE-KX.
Most of the internal blocks are enhanced versions of the current T3 ASIC, including stateless offloads, packet filtering/firewall offload and traffic shaping/media streaming. The T4 has added an embedded 132 port switch, which is important to virtualized servers. The T4 also has an integrated TCAM and large buffer memory on chip, enabling memory-free designs with full performance and features.
Enabling Virtualized Servers, Storage, and HPC
Virtualization is driving large increases in server utilization, which means fewer CPU cycles are available for I/O processing. The embedded switch capability of the T4 enables performance advantages for virtualized environments, supporting up to 128 virtual machines within a single physical server. The T4 supports PCIe single-root I/O virtualization (SR-IOV) and the newest protocols for virtual networking, enabling state-of-the-art virtualization design.
Broadening its support for block storage, Chelsio’s T4 adds support for both partial and full offload of the FCoE protocol in addition to full iSCSI offload. To enable lossless transport of FCoE traffic, the T4 support Priority-based Flow Control (PFC), Enhanced Transmission Selection (ETS) and the Data Center Bridging (DCB) exchange protocol. By simultaneously supporting TOE, iSCSI and FCoE, the T4 enables unified NAS/SAN systems that adapt to and grow with end-customer needs.
For HPC cluster applications, the T4 reduces RDMA latency from about six microseconds in the T3 to two microseconds, which is expected to be lower than InfiniBand DDR solutions. Chelsio has also added UDP-acceleration features to T4 and expects to deliver two microsecond end-to-end latency for UDP packets.
“The networks are converging around 10Gb Ethernet for a number of reasons, and the day is coming when enterprise data center network and storage traffic will be sharing a common infrastructure,” said Kianoosh Naghshineh, president and CEO. “Our fourth generation technology is unmatched in the industry, and our OEM partners understand that offloading protocols such as iWARP and iSCSI requires a reliable, tested TCP engine.”
Pricing and Availability
Designed in 65nm CMOS process technology and packaged in a 27x27mm, 672-pin FCBGA, the T4 dissipates about 7-10W of power depending on configuration. T4 will be available for customer sampling in Q2. For pricing, contact Chelsio Communications at 408-962-3600, or visit the company at www.chelsio.com.
About Chelsio Communications, Inc.
Chelsio Communications is leading the convergence of networking, storage and clustering interconnects with its robust, high-performance and proven unified wire, storage software and appliance technology. Featuring a highly scalable and programmable architecture, Chelsio is shipping 10-Gigabit Ethernet and multi-port Gigabit Ethernet adapter cards, delivering the low latency and superior throughput required for high-performance computing applications. For more information, visit the company online at www.chelsio.com.
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